Future perspective and scaling down roadmap for RF CMOS

Author

Morifuji, E. ; Momose, H.S. ; Ohguro, T. ; Yoshitomi, T. ; Kimijima, H. ; Matsuoka, F. ; Kinugawa, M. ; Katsumata, Y. ; Iwai, H.

Author_Institution

Microelectron Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

1999

fDate

17-19 June 1999

Firstpage

165

Lastpage

166

Abstract

Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100 nm gate length generations.

Keywords

CMOS integrated circuits; UHF integrated circuits; field effect MMIC; impedance matching; integrated circuit manufacture; integrated circuit noise; RF CMOS; RF noise; finger length; gate length; gate width; linearity; matching characteristics; scaling-down; CMOS logic circuits; Character generation; Circuit noise; Fingers; Laboratories; Linearity; Microelectronics; Noise figure; Radio frequency; Roentgenium;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-95-6

Type

conf

DOI

10.1109/VLSIC.1999.797271

Filename

797271

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3217137