Time evolution of the voltage-controlled signal in charge pump PLL applications

Author

Milicevic, Sinisa ; MacEachern, Leonard

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, ON, Canada

fYear

2008

fDate

14-17 Dec. 2008

Firstpage

413

Lastpage

416

Abstract

A transient analysis of the acquisition processes in the loop filter of a frequency synthesizer is presented. A concise mathematical model for the voltage control signal used to tune a voltage controlled oscillator is derived for the transient lock-in process. A frequency synthesizer implemented in a 0.13 Â¿m CMOS technology is used to demonstrate the theoretical analysis. For the particular case examined in this paper, the calculated, simulated, and measured transient signal values differed from each other by less than 7% over the lock-in time interval.

Keywords

charge pump circuits; frequency synthesizers; phase locked loops; transient analysis; voltage-controlled oscillators; CMOS technology; charge pump PLL; frequency synthesizer; loop filter; time evolution; transient analysis; voltage controlled oscillator; voltage-controlled signal; CMOS technology; Charge pumps; Filters; Frequency synthesizers; Mathematical model; Phase locked loops; Signal processing; Transient analysis; Voltage control; Voltage-controlled oscillators; Loop filter; PLL; acquisition process; circuit theory; time domain; voltage-control signal;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2008. ICM 2008. International Conference on

Conference_Location

Sharjah

Print_ISBN

978-1-4244-2369-9

Electronic_ISBN

978-1-4244-2370-5

Type

conf

DOI

10.1109/ICM.2008.5393824

Filename

5393824