DocumentCode
3220192
Title
Automatic testability analysis of boards and MCMs at chip level
Author
Perbost, Marc ; Le Lan, L. ; Landrault, Christian
Author_Institution
Dassault Electonique, France
fYear
1997
fDate
17-19 Nov 1997
Firstpage
36
Lastpage
41
Abstract
Minimising the testing costs of boards and MCMs implies to invest in testability analysis in addition to the use of testing standards (IEEE 1149). In this paper, we propose a testability analysis method for boards and MCMs designed at Dassault Electronique. The actual prototype realised according to this new methodology aims at helping testability expert
Keywords
IEEE standards; circuit analysis computing; design for testability; diagnostic expert systems; measurement standards; minimisation; multichip modules; printed circuit testing; Dassault Electronique; IEEE 1149; MCM; PROLOG; automatic testability analysis; chip level; expert system; minimisation; testing costs; testing standards; Automatic testing; Built-in self-test; Control systems; Costs; Hardware; Performance analysis; Performance evaluation; Probes; Prototypes; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian
Conference_Location
Akita
ISSN
1081-7735
Print_ISBN
0-8186-8209-4
Type
conf
DOI
10.1109/ATS.1997.643913
Filename
643913
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