On energy efficiency of VLSI testing

We discuss the role of power and energy in computation and test efficiency. This is done by the proposal of new computation and test efficiency models that take energy into consideration, followed by the incorporation of these models with the CMOS power consumption model to establish the following observations: (1) low power and high testability need not be competing goals in the design optimization process; (2) high power dissipation during testing may not be an issue, as long as the tester limit is not reached and the chip is not over driven; (3) high-power testing due to high speed and/or high transition activity factor is better in terms of test efficiency; and (4) for a fabricated chip with a prespecified fault coverage, testing energy is roughly constant, independent of the testing power or testing time