Testing for the programming circuit of LUT-based FPGAs

Author

Michinishi, H. ; Yokohira, T. ; Okamoto, T. ; Inoue, T. ; Fujiwara, H.

Author_Institution

Dept. of Inf. Technol., Okayama Univ., Japan

fYear

1997

fDate

17-19 Nov 1997

Firstpage

242

Lastpage

247

Abstract

The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware

Keywords

SRAM chips; field programmable gate arrays; logic CAD; logic testing; shift registers; table lookup; FPGA; SRAM; configuration memory cell array; control circuit; fault model; look-up table; programming circuit; shift registers; Automatic speech recognition; Circuit faults; Circuit testing; Field programmable gate arrays; Logic circuits; Logic programming; Logic testing; Programmable logic arrays; Random access memory; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian

Conference_Location

Akita

ISSN

1081-7735

Print_ISBN

0-8186-8209-4

Type

conf

DOI

10.1109/ATS.1997.643965

Filename

643965

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3220933