A XOR-tree based technique for constant testability of configurable FPGAs

Author

Huang, W.-K. ; Zhang, M.Y. ; Meyer, F.J. ; Lombardi, F.

Author_Institution

Dept. of Electron. Eng., Fudan Univ., Shanghai, China

fYear

1997

fDate

17-19 Nov 1997

Firstpage

248

Lastpage

253

Abstract

This paper presents a novel approach for testing and diagnosing configurable field programmable gate arrays (FPGAs). The proposed approach is row-based and uses a two-session procedure. The approach arranges some logic blocks to be programmed as XOR-tree (or chain, or cascade) in the first session. The XOR-tree is effectively used as test vehicle for observability. The roles of the CLBs are inverted in the second session. It is shown that the proposed testing arrangement requires a number of tests independent of the number of CLBs in the FPGA (i.e. C-testability is accomplished). Routing is kept local, and compatibility for a CAD implementation is also accomplished

Keywords

SRAM chips; design for testability; fault location; field programmable gate arrays; logic testing; C-testability; CAD implementation; FPGA; SRAM; XOR-tree; cascade; chain; compatibility; configurable FPGA; configurable field programmable gate arrays; constant testability; fault model; logic blocks; observability; routing; Built-in self-test; Circuit faults; Circuit testing; Field programmable gate arrays; Logic testing; Observability; Pipeline processing; Programmable logic arrays; Routing; Sequential analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian

Conference_Location

Akita

ISSN

1081-7735

Print_ISBN

0-8186-8209-4

Type

conf

DOI

10.1109/ATS.1997.643966

Filename

643966