Title :
Random pattern testable design with partial circuit duplication
Author :
Yokoyama, Hiroshi ; Wen, Xiaoqing ; Tamatoto, H.
Author_Institution :
Dept. of Inf. Eng., Akita Univ., Japan
Abstract :
The advantage of random testing is that test application can be performed at a low cost in the BIST scheme. However, not all circuits are random pattern testable. In this paper, we present a method for improving random pattern testability of logic circuits by partial circuit duplication. The basic idea is to detect random pattern resistant faults by using the difference between the duplicated part of a circuit and the original part. Experimental results on benchmark circuits show that high fault coverage can be achieved with a very small amount of hardware overhead
Keywords :
built-in self test; design for testability; fault location; logic design; logic testing; random processes; BIST; benchmark circuits; cost; fault coverage; partial circuit duplication; random pattern testability; testable design; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Performance evaluation;
Conference_Titel :
Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian
Conference_Location :
Akita
Print_ISBN :
0-8186-8209-4
DOI :
10.1109/ATS.1997.643982