Title :
Built-in self-test for multi-port RAMs
Author :
Wu, Yuejian ; Gupta, Sanjay
Author_Institution :
Northern Telecom, Ottawa, Ont., Canada
Abstract :
Most multi-port memory BIST algorithms treat the memory as multiple individual single-port memories and test each independently using the algorithms developed for single-port RAMs. A major problem with this approach is the lack of coverage for multi-port specific defects, such as inter-port interferences due to shorts across ports. This paper proposes a novel BIST algorithm for multi-port RAMs that detects both The conventional single-port faults as well as inter-port shorts. The proposed algorithm performs a conventional single-port test such as MARCH (1991) or SMARCH (1990) on one port of the memory and simultaneously performs an inter-port test on all other ports. The algorithm does not impose any extra test time and requires the addition of only a few gates to a conventional single-port BIST controller, independently of the size of the memory
Keywords :
built-in self test; electric noise measurement; fault location; integrated memory circuits; interference (signal); random-access storage; short-circuit currents; MARCH; SMARCH; built-in self-test; inter-port interference; memory BIST algorithms; multi-port RAM; multi-port defects; shorts; single-port faults; Application specific integrated circuits; Built-in self-test; Design methodology; Fault detection; Interference; Performance evaluation; Random access memory; Read-write memory; System testing; Telecommunications;
Conference_Titel :
Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian
Conference_Location :
Akita
Print_ISBN :
0-8186-8209-4
DOI :
10.1109/ATS.1997.643989