Title :
Fault-tolerant cube-connected cycles capable of quick broadcasting
Author_Institution :
Inf. & Commun. Syst. Labs., NTT, Tokyo, Japan
Abstract :
The construction of fault-tolerant processor arrays with interconnections of cube-connected cycles (CCCs) by using an advanced spare-connection scheme for k-out-of-n redundancies called “generalized additional bypass linking” is described. The connection scheme uses bypass links with wired OR connections to spare processing elements (PEs) without external switches, and can reconfigure complete arrays by tolerating faulty portions in these PEs and links. The spare connections are designed as a node-coloring problem of a CCC graph with a minimum distance of 3: the chromatic numbers corresponding to the number of spare PE connections were evaluated theoretically. The proposed scheme can be used for constructing various k-out-of-n configurations capable of quick broadcasting by using spare circuits, and is superior to conventional schemes in terms of extra PE connections and reconfiguration control. In particular, it allows construction of optimal r-fault-tolerant configurations that provide r spare PEs and r extra connections per PE for CCCs with 4*x PEs (x: integer) in each cycle
Keywords :
fault tolerant computing; graph colouring; hypercube networks; reconfigurable architectures; redundancy; CCC graph; chromatic numbers; cube-connected cycle; fault-tolerant processor array; generalized additional bypass linking; interconnections; k-out-of-n redundancy; node coloring; quick broadcasting; reconfiguration control; spare processing elements; Broadcasting; Circuit faults; Communication systems; Fault tolerance; Fault tolerant systems; Integrated circuit interconnections; Joining processes; Laboratories; Redundancy; Switches;
Conference_Titel :
Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-3639-9
DOI :
10.1109/ICISS.1996.552443