The design of low-power CMOS pipelined-burst SRAM

Author

Lee, C.L. ; Wagiran, R. ; Suparjo, B.S. ; Sidek, Roslina

Author_Institution

Dept. of Electr. & Electron. Eng., Putra Malaysia Univ., Serdang

fYear

2000

fDate

2000

Firstpage

241

Lastpage

244

Abstract

This paper presents a low power pipelined-burst synchronized static random access memory. Low-power techniques are reviewed for capacitance reduction by using a divided word-line structure, and for operating voltage reduction by using a current-mode sensing technique for the sense amplifier. The SRAM is designed with address burst mode operation and selective byte write operation

Keywords

CMOS memory circuits; SRAM chips; capacitance; current-mode circuits; integrated circuit design; low-power electronics; pipeline processing; SRAM design; address burst mode operation; capacitance reduction; current-mode sensing technique; divided word-line structure; low power pipelined-burst synchronized static random access memory; low-power CMOS pipelined-burst SRAM design; low-power techniques; operating voltage reduction; selective byte write operation; sense amplifier; Capacitance; Communication system control; Counting circuits; Decoding; Energy consumption; Logic devices; Power dissipation; Power system reliability; Random access memory; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 2000. Proceedings. ICSE 2000. IEEE International Conference on

Conference_Location

Guoman Port Dickson Resort

Print_ISBN

0-7803-6430-9

Type

conf

DOI

10.1109/SMELEC.2000.932471

Filename

932471