• DocumentCode
    3225255
  • Title

    How many entries we need in miss handling architectures of L1 and L2 cache?

  • Author

    Liu, De-feng ; Pan, Guo-teng ; Xie, Lun-guo ; Liu, Bin

  • Author_Institution
    Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
  • fYear
    2011
  • fDate
    27-29 May 2011
  • Firstpage
    501
  • Lastpage
    504
  • Abstract
    Recently-proposed processor micro-architectures for high Memory Level Parallelism (MLP) harvest substantial performance gains. Unfortunately, Miss-Handling architectures (MHAs) of current cache hierarchies are too limited to support the requirement of high MLP system. This paper proves the number relation of MHA entries between L1 and L2 cache, presents an algorithm to forecast the supremum of MHA entries. The analysis results present the MHA quantitative requirements for MLP processors. At last we valid the proved relation in experiment.
  • Keywords
    cache storage; parallel memories; parallel processing; L1 cache; L2 cache; memory level parallelism; miss-handling architecture; processor microarchitecture; Benchmark testing; Memory-level parallelism; Miss-Handling architectures; cache; memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communication Software and Networks (ICCSN), 2011 IEEE 3rd International Conference on
  • Conference_Location
    Xi´an
  • Print_ISBN
    978-1-61284-485-5
  • Type

    conf

  • DOI
    10.1109/ICCSN.2011.6013954
  • Filename
    6013954
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3225255