Title :
HiveFlex Video VSP1 Demonstration
Author :
Beric, Aleksandar ; Pinto, Carlos
Abstract :
This work presents a real-time demonstrator system for the VSP1 Tile. The complete 8-way SIMD VSP1 Tile is implemented on the demonstration platform based on the Xilinx Virtex2 XC2V8000 FPGA chip. The application running on a VSP1 Tile is spatial up-scaling. This is a challenging application since it is based on a pixel-based algorithm using content adaptive filtering. The FPGA running on 25 MHz is capable of achieving 17.3 fps for input sequence (320*192) producing four times bigger output sequence (640*384)
Keywords :
adaptive filters; field programmable gate arrays; parallel processing; real-time systems; sequences; video signal processing; 25 MHz; 8-way SIMD VSP1 Tile; HiveFlex Video; Xilinx Virtex2 XC2V8000 FPGA chip; content adaptive filtering; field programmable gate array; pixel-based algorithm; real-time demonstrator system; sequence; video signal processing; Adaptive filters; Bandwidth; Computer architecture; Engines; Field programmable gate arrays; Filtering algorithms; HDTV; High definition video; Software maintenance; Tiles;
Conference_Titel :
Multimedia, 2006. ISM'06. Eighth IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7695-2746-9
DOI :
10.1109/ISM.2006.82
