SDR structure based CFO estimation and compensation circuit for OFDM systems using reconfigurable CORDIC FPGA modules

In this paper, a software defined radio (SDR) structure based carrier frequency offset (CFO) estimation and compensation circuit is designed for an orthogonal frequency division multiplexing (OFDM) system using the reconfigurable coordinate rotation digital computer (CORDIC) field programmable gate array (FPGA) rotation and vectoring circuit modules. The SDR architecture of the CFO estimation and compensation circuit and the program flow of the CORDIC FPGA modules are presented. The required processing time and hardware reconfiguration function are our major design considerations. The experimental results demonstrate that the designed CFO estimation and compensation circuit implemented with a 10 MHz clock FPGA chip can reduce the residual CFO to an acceptable range within 1.5μsec.