Efficient DFV-aware flip-flops

The advanced nanometer circuits are susceptible to errors caused by process, voltage, and temperature (PVT) variation and single event upset (SEU). The state-of-the-art variation-aware flip-flops (FFs) only detect the errors with high overheads. We propose two design-for-variability (DFV)-aware flip-flops (edge-sensitive FF and pulsed FF) which can handle reliability problems efficiently. The HSPICE simulation results show that the proposed DFV-aware FFs have better performance compared to existing FFs.