CSP limitations imposed by mainboard technology limits

Author

Rates, Jim

Author_Institution

Chip Supply Inc., Orlando, FL, USA

fYear

1998

fDate

15-17 Apr 1998

Firstpage

543

Lastpage

545

Abstract

It is possible at present to assemble and test chip scale packaged (CSP) die in bump array pitches down to 0.4 mm. It is also possible to assemble and test bumped die in pitches below 150 μm. However, the volume users of these products assemble on laminate substrates made of FR4, FR5, BT or similar materials. The state of the art for lines, spaces, and through-holes limits the effectiveness of downsizing die packages. This paper examines the matches between these technologies and future matches between CSP pitches and mainboard technologies

Keywords

integrated circuit design; integrated circuit packaging; integrated circuit testing; laminates; microassembling; BT resin laminates; CSP; CSP pitch; FR4 laminates; FR5 laminates; bump array pitch; chip scale package; chip scale packaged die assembly; chip scale packaged die test; circuit line/space patterns; die package downscaling; laminate substrates; mainboard technology; through-holes; Assembly; Chip scale packaging; Electronics packaging; Laminates; Multichip modules; Routing; Semiconductor device manufacture; Semiconductor device packaging; Space technology; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Multichip Modules and High Density Packaging, 1998. Proceedings. 1998 International Conference on

Conference_Location

Denver, CO

Print_ISBN

0-7803-4850-8

Type

conf

DOI

10.1109/ICMCM.1998.670839

Filename

670839