Title :
ADC clock jitter measurement and correction using a stochastic TDC
Author :
Fan, Chi-Wei ; Wu, Jieh-Tsorng
Author_Institution :
Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
The jitter of the sampling clock of an analog-to-digital converter (ADC) is measured by a stochastic time-to-digital converter (TDC). The measured jitter data are used to correct the ADC sampling error and improve its signal-to-noise ratio (SNR). The same ADC is used to calibrate the TDC in the background. Both the TDC and the ADC operate at a sampling rate of 80 MS/s. Fabricated in a 65 nm CMOS technology, the TDC consists of 127 timing comparators. The proposed jitter correction technique achieves an equivalent sampling jitter root-mean-squared value (rms) of 4 ps when the jitter rms of the original sampling clock is 8.2 ps.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; clocks; jitter; time measurement; ADC clock jitter measurement; ADC sampling error; CMOS technology; SNR; analog-to- digital converter; jitter correction technique; root-mean-squared value; signal-to-noise ratio; size 65 nm; stochastic TDC; stochastic time-to-digital converter; timing comparators; Clocks; Delay; Delay lines; Jitter; Semiconductor device measurement; Signal to noise ratio;
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
DOI :
10.1109/APCCAS.2010.5774884