Design issues and optimization in DisplayPort link layer implementation

Nowadays, the advanced digital display technology makes display devices support extreme high quality video like full HD. In order to support the quality, a communication interface of the display devices must provide a high bandwidth in video transmission. The DisplayPort, as one of the solutions, was proposed as an industry standard to transmit high color depths, refresh rates and display resolution. In this paper, we present several optimization methods from our experience to prototype a datalink layer of the DisplayPort interface based on the DisplayPort standard version 1.1a of VESA. Also, we show that our system consumes 205.3K logic cells and 55.6mW power with Samsung 0.13um library.