Clock-gated and low-power standard cell library for ISFET Two-Point Calibration processor chip

This paper presents a novel clock gate cell that employs header and footer devices to isolate the transistor connected to clock signal. This new clock gate is called Low Internal Power Clock Gate (LIPCG), and saves power up to 81.77% over conventional clock gate during sleep operation. Moreover, this LIPCG is added into our in-house library which is based on TSMC 0.35um CMOS technology. The power performance of this new set of library is evaluated, by implementing a Two-Point Calibration (TPC) processor with Sleep Controller (SC) for Ion-Sensitive Field-Effect Transistor (ISFET). Event-driven power analysis indicated a power saving of 87.89% during the sleep mode of TPC chip. Availability of this clock-gated low-power standard cell library allows us to optimize the power consumptions of our portable ISFET systems, such as pH meters and remote sensor nodes for continuous water quality and environment monitoring applications.