ESP verification for custom SRAM array design

Author

Du Hongyan ; Tan Manqiong ; Tian Xinhua ; Xu Hongliang

Author_Institution

Dept. of Comput. Sci. & Technol., Changsha Univ., Changsha, China

fYear

2009

fDate

25-28 July 2009

Firstpage

1889

Lastpage

1892

Abstract

ESP-CV is a symbolic simulation-based formality verification tool intended to perform custom equivalence(EQ) checking and provide functional verification coverage for full-custom IC design. This paper introduced the basic principle and work flow of ESP verification firstly, and then the ESP verification method and flow of our custom SRAM array design was demonstrated.

Keywords

SRAM chips; digital circuits; ESP verification; IC design; custom SRAM array design; perform custom equivalence checking; symbolic simulation-based formality verification tool; Circuit simulation; Computer science; Delay; Discrete event simulation; Electrostatic precipitators; Integrated circuit modeling; Random access memory; SPICE; Semiconductor device modeling; Testing; Computer simulation; Constraints; Custom SRAM Array; EQ Checking; ESP; Itegrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science & Education, 2009. ICCSE '09. 4th International Conference on

Conference_Location

Nanning

Print_ISBN

978-1-4244-3520-3

Electronic_ISBN

978-1-4244-3521-0

Type

conf

DOI

10.1109/ICCSE.2009.5228237

Filename

5228237

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3230618