DocumentCode
3230709
Title
An improved 32-bit carry-lookahead adder with Conditional Carry-Selection
Author
Ping-Hua Chen ; Juan Zhao ; Guo-bo Xie ; Yi-Jun Li
Author_Institution
Fac. of Comput., Guangdong Univ. of Technol., Guangzhou, China
fYear
2009
fDate
25-28 July 2009
Firstpage
1911
Lastpage
1913
Abstract
An improved 32-bit carry-lookahead adder (CLA) with conditional carry-selection (CSS) is proposed in this paper. The new adder is compared with serial adder and pure carry-lookahead adder. The three adders is simulated in FPGA circuits, the results show that the propagation time of the carry of the new 32-bit adder is reduced 26% compared with Serial Adder and 3.17% with pure Carry-Lookahead Adder.
Keywords
adders; field programmable gate arrays; 32-bit carry-lookahead adder; FPGA circuits; conditional carry-selection; serial adder; Adders; Cascading style sheets; Circuit simulation; Computational modeling; Computer science; Computer science education; Delay effects; Erbium; Field programmable gate arrays; Logic; CLA; CSS; adder;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Science & Education, 2009. ICCSE '09. 4th International Conference on
Conference_Location
Nanning
Print_ISBN
978-1-4244-3520-3
Electronic_ISBN
978-1-4244-3521-0
Type
conf
DOI
10.1109/ICCSE.2009.5228242
Filename
5228242
Link To Document