A 10-bit 1.25GSample/s partially-segmented D/A Converter for Ultra Wide-Band communication system

This paper proposes a 10-bit 1.25GSample/s partially-segmented D/A converter for Ultra Wide-Band communication system fabricated in a digital 0.18um 1-poly 6-metal standard CMOS technology. To achieve low power consumption and small chip area with good linearity we employ partially segmented D/A converter architecture. Also, we use deglitch circuit and common-centroid layout scheme in the current cell matrix to obtain good linearity of the converter. Simulation results show that the implemented D/A converter has 73dB SFDR at 426MHz input signal with 49.5mW power consumption. The maximum integral nonlinearity (INL) is 0.3LSB and the maximum differential nonlinearity (DNL) is 0.15LSB. The active chip area is 2.21mm².