Title :
A mathematical model for defect impact based on in-line vs test data correlations
Author :
Fernandez, Almudena ; Lorenzo, Alfonso ; Cruceta, Sergio ; Oter, David ; James, D.A.
Author_Institution :
Lucent Technol. Microelectron., Madrid, Spain
Abstract :
This paper describes the methodology used to build a mathematical model to determine the yield impact of particles in integrated circuits, known as “Kill Ratio” (KR). The Kill Ratio represents the probability that a certain particle of a given size at a given inspection step will cause the failure of the device. These numbers are calculated based on actual particle data, collected on a routine basis inside the clean room, and the yield data after electrical test of finished product. The objective we pursue with a mathematical model is to find a simple expression for the Kill Ratio, based on defect sizes, which can be related to some geometrical characteristic of the device layout. While the procedure to calculate the Kill Ratio from particle and probe data is fundamentally statistical (that is, enough data must be collected to ensure the accuracy of these numbers), a mathematical expression based on design parameters would allow us to calculate the Kill Ratio of product with very low volume, such as prototypes, new products, technology qualification products, etc. This type of information will speed up the yield improvement cycle, as well as to the time to “yield entitlement” for the new products and technologies introduction. The paper gives the detail of the results obtained with this model and also some future plans for refining the model
Keywords :
inspection; integrated circuit modelling; integrated circuit yield; probability; statistical analysis; IC manufacture; defect impact; defect sizes; design parameters; device failure; device layout; electrical test; geometrical characteristic; inline versus test data correlations; inspection step; integrated circuits; kill ratio; mathematical model; particle data collection; probability; yield data; yield improvement cycle; Circuit testing; Failure analysis; Inspection; Integrated circuit modeling; Integrated circuit technology; Integrated circuit testing; Integrated circuit yield; Mathematical model; Probes; Yield estimation;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI
Conference_Location :
Boston, MA
Print_ISBN :
0-7803-5217-3
DOI :
10.1109/ASMC.1999.798189