Title :
Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs
Author :
Kobayashi, Kazutoshi ; Onodera, Hidetoshi
Author_Institution :
Kyoto Univ., Kyoto
Abstract :
Error rates on an LSI are increasing according to the Moore´s law. Now is the time to start incorporating error-tolerant design methodologies. This paper introduces sources of failures in semiconductor devices, levels of dependability according to applications of devices and some circuit-level techniques to detect or recover faults after shipping.
Keywords :
fault tolerance; large scale integration; semiconductor device testing; LSI; Moore law; circuit-level technique; error-tolerant design; semiconductor device failure; Aging; Auditory displays; Cellular phones; Circuits; Degradation; Electric breakdown; Error correction; Liquid crystal displays; Moore´s Law; Semiconductor devices;
Conference_Titel :
Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-1921-0
Electronic_ISBN :
978-1-4244-1922-7
DOI :
10.1109/ASPDAC.2008.4484065
