DocumentCode
323259
Title
Timing and control requirements for a 32-channel AMU-ADC ASIC for the PHENIX detector
Author
Emery, M.S. ; Ericson, M.N. ; Britton, C.L., Jr. ; Smith, M.C. ; Frank, S.S. ; Young, G.R. ; Allen, M.D. ; Clonts, L.G.
Author_Institution
Oak Ridge Nat. Lab., TN, USA
fYear
1997
fDate
9-15 Nov 1997
Firstpage
651
Abstract
A custom CMOS Application Specific Integrated Circuit (ASIC) has been developed consisting of an analog memory unit (AMU) and analog to digital converter (ADC), both of which have been designed for applications in the PHENIX experiment. This IC consists of 32 pipes of analog memory with 64 cells per pipe. Each pipe also has its own ADC channel. Timing and control signal requirements for optimum performance are discussed in this paper
Keywords
CMOS analogue integrated circuits; analogue storage; analogue-digital conversion; mixed analogue-digital integrated circuits; nuclear electronics; pipeline processing; ADC channel; AMU-ADC ASIC; CMOS Application Specific Integrated Circuit; PHENIX detector; analog memory; analog memory unit; analog to digital converter; control signal requirements; timing; Analog memory; Application specific integrated circuits; Capacitors; Clocks; Detectors; Laboratories; Read-write memory; Registers; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Nuclear Science Symposium, 1997. IEEE
Conference_Location
Albuquerque, NM
ISSN
1082-3654
Print_ISBN
0-7803-4258-5
Type
conf
DOI
10.1109/NSSMIC.1997.672666
Filename
672666
Link To Document