Designing 3.125 GHz bang-bang PLL for Clock Recovery in 6.25 Gbps Backplane Communication Receiver

Author

Mingzhu, Zhou ; Lingling, Sun ; Guangyi, Wang ; Jun, Liu ; Jingcai, Wen ; Jie, Wang

Author_Institution

Inst. of Electron. & Inf. Eng., Hangzhou Dianzi Univ., Hangzhou, China

fYear

2010

fDate

8-11 May 2010

Firstpage

639

Lastpage

642

Abstract

A 3.125 GHz Clock Recovery (CR) circuit used in the 6.25Gbps SerDes for Backplane Communication Receiver is described. Bang-bang PLL architecture is utilized for its high operation speed. An Alexander phase detector (PD) and a LC voltage-control oscillator (VCO) are involved in the circuit. The behavior of the nonlinear bang-bang PLL is modeled to give approximate evaluation of the loop stability. The circuit has been implemented in a standard 0.18 μm CMOS technology. The test result indicates that the frequency of the VCO is from 3 GHz to 3.35 GHz, the voltage gain is 270 MHz/V, and the phase noise is -118.38 dBc/Hz @1 MHz. The chip consumes less than 81 mW with 1.8 V power supply, and occupies 0.5 mm² area.

Keywords

CMOS integrated circuits; phase locked loops; radio receivers; synchronisation; voltage-controlled oscillators; Alexander phase detector; CMOS technology; LC voltage-control oscillator; VCO; backplane communication receiver; bang-bang PLL; clock recovery circuit; data transmission systems; frequency 3.125 GHz; power 81 mW; voltage 1.8 V; Backplanes; CMOS technology; Chromium; Circuits; Clocks; Detectors; Phase detection; Phase locked loops; Semiconductor device modeling; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter Wave Technology (ICMMT), 2010 International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-5705-2

Type

conf

DOI

10.1109/ICMMT.2010.5525007

Filename

5525007