Title :
Sub-0.25 μm ultra-thin SOI CMOS with a single N+ gate process for low-voltage and low-power applications
Author :
Raynaud, C. ; Faynot, O. ; Pelloie, J.L. ; Tedesco, S. ; Ullmann, B. ; Dunne, B. ; Guegan, G. ; Lerme, M.
Author_Institution :
CEA, Centre d´´Etudes Nucleaires de Grenoble, France
fDate :
30 Sep-3 Oct 1996
Abstract :
Fully-depleted (FD) 0.2 μm SOI CMOS devices have been fabricated with a single N+ gate process. As an ultra-thin film is required to optimize fully-depleted 0.2 μm SOI devices, a recessed channel structure has been used in order to prevent any contact problems. Dynamic performance has been demonstrated down to 1 V supply voltage with 0.25 μm ring oscillators (propagation delay of 80 ps at 1.5 V) and 0.2 μm 16 K SRAM (access time of 6 ns at 1.5 V). These results show that 0.2 μm FD SOI devices meet the requirements for low voltage and low power applications
Keywords :
CMOS digital integrated circuits; MOSFET; VLSI; delays; integrated circuit measurement; silicon-on-insulator; 0.2 micron; 1 to 1.5 V; 6 ns; 80 ps; SRAM; access time; fully-depleted devices; low-power applications; low-voltage applications; propagation delay; recessed channel structure; ring oscillators; single N+ gate process; ultra-thin SOI CMOS; CMOS process; Capacitance; Inverters; Lithography; MOSFET circuits; Propagation delay; Random access memory; Ring oscillators; Silicon; Threshold voltage;
Conference_Titel :
SOI Conference, 1996. Proceedings., 1996 IEEE International
Conference_Location :
Sanibel Island, FL
Print_ISBN :
0-7803-3315-2
DOI :
10.1109/SOI.1996.552503
