Title :
Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access
Author :
Marinissen, Erik Jan
Author_Institution :
IMEC vzw, Leuven, Belgium
Abstract :
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) have many attractive benefits and hence are quickly gaining ground. Testing such products for manufacturing defects is still fraught with many challenges. This paper provides an overview of those challenges and their emerging solutions, categorized in the areas of (1) test flows, (2) test contents, and (3) test access.
Keywords :
design for testability; integrated circuit testing; three-dimensional integrated circuits; 3D-SIC; TSV-based 3D stacked IC; test access; test content; test flow; three-dimensional stacked IC; through-silicon vias; Conferences; Probes; Stacking; Testing; Three dimensional displays; Through-silicon vias;
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
DOI :
10.1109/APCCAS.2010.5775087
