• DocumentCode
    3233291
  • Title

    Ab initio Study of Boron Pile-up at the Si(001)/SiO2 Interface

  • Author

    Zhang, Jinyu ; Ashizawa, Yoshio ; Oka, Hideki ; Kaneta, Chioko ; Yamazaki, Takahiro

  • Author_Institution
    Fujitsu R&D Center Co. Ltd., Beijing
  • fYear
    2006
  • fDate
    6-8 Sept. 2006
  • Firstpage
    143
  • Lastpage
    146
  • Abstract
    We studied the atomistic structure of boron atom at the Si(001)/SiO2 interface using ab initio calculation method to investigate the mechanism of boron pile-up at the interface. We found that, if there is no defects, such as oxygen vacancy, at the interface, no stable sites of B would appear at Si/SiO2 interface and SiO2 layer, thus indicating that boron in silicon will only diffuse to the interface, but not segregate across the interface, unless additional defects or impurities exist. By introducing oxygen vacancy and H bonds, we found some stable configurations at Si/SiO2 interface, which can support the mechanism of boron segregation at Si(001)/SiO2 interface. Therefore, we assume that vacancy of O and H bonds may play a crucial role in segregation by opening additional trapping sites. Furthermore, we also found the largest energy difference between B at Si/SiO2 interface and that in deep bulk Si is about 2.9eV, which is in agreement with experimental boron activation energy of emission from Si/SiO2 value of 2.64eV
  • Keywords
    ab initio calculations; boron; elemental semiconductors; impurities; interface structure; segregation; semiconductor-insulator boundaries; silicon; silicon compounds; vacancies (crystal); H bonds; Si(001) surface; Si:B-SiO2; ab initio calculation method; atomistic structure; boron activation energy; boron pile-up; boron segregation; impurities; interface structure; oxygen vacancy; Atomic layer deposition; Boron; Chaos; Fabrication; Hydrogen; Impurities; Laboratories; MOSFETs; Research and development; Silicon; Si/SiO2 interface; ab initio; boron; pile-up;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Simulation of Semiconductor Processes and Devices, 2006 International Conference on
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    1-4244-0404-5
  • Type

    conf

  • DOI
    10.1109/SISPAD.2006.282858
  • Filename
    4061601