An improved I/O buffer correlation methodology between silicon and the SPICE model

High-performance systems that involve tightly-constrained design parameters create significant challenges for board designers. The ability to simulate a complex design before laying out the board has become a critical factor in the success of a project. From the manufacturers´ standpoint, releasing a SPICE model involves the risk of exposing confidential circuit netlists. Altera provides the IBIS model, which is a behavioral method of modeling I/O buffers derived from the SPICE model. Extensive correlation between the SPICE model and silicon increases reliability and accuracy of IBIS generation. However, long correlation timeline and various factors such as modeling complexity jeopardize the timely release of a model to customers. This paper demonstrates Altera´s I/O buffer silicon versus model correlation evolution from its infancy to where it is today. Research on correlation methodology was carried out to minimize the PCB interconnect effect that complicates these modeling efforts. Statistical data collection and analysis in an automated environment adds value to increase customers´ confidence in our IBIS model. The simplification efforts benefit Altera and the industry by increasing correlation efficiencies, reducing material costs, improved time to market, and the providing highly reliable IBIS model to customers.