Title :
Modeling technique for simulation time speed-up of performance computation in transaction level models
Author :
Le Nours, S. ; Barreteau, A. ; Pasquier, O.
Author_Institution :
IREENA, Univ Nantes, Nantes, France
Abstract :
Modeling embedded systems at transaction level facilitates the architecting of hardware and software resources according to non-functional requirements. Raising the level of abstraction, Transaction Level Modeling (TLM) represents a good compromise between modeling accuracy and simulation speed. However, in complex pipelined architectures, the efficiency of exploration and performance evaluation is limited by the number of involved transactions and by the various non-functional properties to assess. In this paper we propose a technique to improve the creation of transaction level models and the description of properties related to resources of the system architecture. This technique is based on the separation of concerns between the evolution of a system model at transaction level and the computation of non-functional properties. The considered case study is a wireless communication receiver based on the Long Term Evolution (LTE) protocol. The proposed technique is used to evaluate the related computing complexity according to various system configurations.
Keywords :
Long Term Evolution; embedded systems; hardware-software codesign; modelling; performance evaluation; pipeline processing; protocols; radio receivers; computational complexity; embedded systems modeling; long term evolution protocol; performance evaluation; pipelined architecture; system architecture; system configuration; transaction level modeling; wireless communication receiver;
Conference_Titel :
Specification & Design Languages (FDL 2010), 2010 Forum on
Conference_Location :
Southampton
DOI :
10.1049/ic.2010.0142