Title :
Knowledge extraction techniques for expert system assisted wafer screening
Author :
Khera, D. ; Cresswell, M.W. ; Linholm, L.W. ; Ramanathan, G. ; Buzzeo, J. ; Nagarajan, A.
Author_Institution :
NIST, Gaithersburg, MD, USA
Abstract :
The authors describe a procedure for using induction-based classification techniques for identifying relationships between work-in-process (WIP) test structure data and future IC yield at wafer test on a wafer-by-wafer or lot-by-lot basis. The relationships are extracted from databases of previously processed WIP wafer test structure measurements and final wafer yield. They are presented in the form of rules relating WIP data to final yield. It is further shown that these rules, when incorporated into expert systems, can advise the human operator responsible for screening wafers which are likely to produce submarginal yield if processed to completion. These rules also identify the WIP test structure parameters and values which have historically provided the highest and lowest final wafer yields
Keywords :
expert systems; inspection; integrated circuit manufacture; integrated circuit testing; knowledge based systems; production testing; WIP test structure parameters; expert system assisted wafer screening; final wafer yields; future IC yield; identifying relationships; induction-based classification techniques; rules relating WIP data to final yield; screening wafers; test structure data; Cost function; Expert systems; Frequency; Integrated circuit modeling; Integrated circuit testing; Manufacturing processes; NIST; Semiconductor device manufacture; Semiconductor device modeling; Virtual manufacturing;
Conference_Titel :
Semiconductor Manufacturing Science Symposium, 1990. ISMSS 1990., IEEE/SEMI International
Conference_Location :
Burlingame, CA
DOI :
10.1109/ISMSS.1990.66127