Title :
New structure for adder with improved speed, area and power
Author :
Fatemeh, K.H. ; Horestani, Ali K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Isfahan Univ. of Technol., Isfahan, Iran
Abstract :
Adders are the main parts of processing circuits and play an important role in all mathematical operations like subtraction, multiplication, division, etc. Carry Look ahead Adder (CLA) is one of the fastest adder structures that is widely used in the processing circuits. In this article a new structure for adder is proposed. The results show that compared to the previous common Modified Carry Look ahead Adder (MCLA) structure, the proposed structure has very smaller on-chip area and delay and also it has lower power consumption. Using the proposed structure a 64-bit adder is designed and results are presented. The circuit is designed in TSMC 0.18μm CMOS technology with 1.8v power supply and simulated with HSPICE.
Keywords :
CMOS integrated circuits; mathematical analysis; microprocessor chips; power aware computing; CLA; CMOS technology; MCLA; area improvement; carry look ahead adder; mathematical operations; modified carry look ahead adder; new structure; power consumption; power improvement; processing circuits; speed improvement; Adders; Computers; Delay; Power demand; Silicon; System-on-a-chip; Transistors; Area; Carry Look ahead Adder; Delay; Ripple Carry Adder;
Conference_Titel :
Networked Embedded Systems for Enterprise Applications (NESEA), 2011 IEEE 2nd International Conference on
Conference_Location :
Fremantle, WA
Print_ISBN :
978-1-4673-0495-5
DOI :
10.1109/NESEA.2011.6144953
