Abstract :
Summary form only given. Scaling down of device sizes and supply voltage requires a commensurate scaling of transistor threshold voltage to maintain high performance. Such scaling leads to exponential increase in leakage current, decreased noise immunity for high speed circuits, and increased defects. In this tutorial we present design and test techniques to combat these problems in the deep sub-micron regime for bulk, SOI and future technologies. We consider the following issues in turn: 1. Device scaling and its impact on sub-threshold and gate leakage current, interconnects, and noise immunity. 2. Low voltage circuit design under high intrinsic leakage, leakage monitoring and control techniques, effective transistor stacking, multi-threshold CMOS, dynamic threshold CMOS, SOI implications. Design of low leakage data-paths and caches. 3. SOI design - comparison with bulk, logic and memory design, asynchronous design. 4. Copper, low k, and impact of low k on performance. 5. Future technologies - double gate fully depleted SOI, FIN FET, and 3D SOI. 6. Noise modeling and analysis for high-speed precharge-evaluate circuits such as domino. Noise tolerant circuit design styles - skewed CMOS, noise tolerant domino, layout styles for high noise immunity. 7. Iddq testing of circuits with high intrinsic leakage elta Iddq, two parameter tests. Idd waveform analysis.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; integrated circuit noise; integrated circuit testing; leakage currents; logic design; logic testing; low-power electronics; silicon-on-insulator; threshold logic; 3D SOI; CMOS circuit design; FIN FET; Idd waveform analysis; SOI; VLSI; asynchronous design; copper interconnects; device size scaling; double gate fully depleted SOI; dynamic threshold CMOS; gate leakage current; leakage control; leakage monitoring; logic design; low leakage caches; low leakage data-paths; low voltage circuit design; low-k dielectrics; memory design; multi-threshold CMOS; noise analysis; noise immunity; noise modeling; noise tolerant domino; precharge-evaluate circuits; skewed CMOS; supply voltage scaling; transistor stacking; transistor threshold voltage; two parameter tests; CMOS memory circuits; CMOS technology; Circuit noise; Circuit synthesis; Circuit testing; Integrated circuit interconnections; Leakage current; Low voltage; Monitoring; Threshold voltage;