Title :
Testing embedded cores and SOCs-DFT, ATPG and BIST solutions
Author :
Parekhji, Rubin A.
Author_Institution :
Texas Instruments, India
Abstract :
Summary form only given. This tutorial presents a range of design and test techniques and considerations for incorporating high level testability into high performance SOC designs, constructed using embedded cores. Different solutions are proposed around DFT, ATPG and BIST techniques, and their implementation explained from the design and test viewpoints, for different components of SOCs. Capabilities of test automation tools to aid such implementations are explained alongside. Finally, a framework for design planning to assist in test logic implementation and validation, to meet aggressive design cycle times, is presented.
Keywords :
automatic test pattern generation; boundary scan testing; built-in self test; design for testability; industrial property; integrated circuit design; integrated circuit testing; logic design; logic testing; system-on-chip; ATPG; BIST; DFT; IP cores; SOC components; SOC implementation; design cycle times; design planning framework; embedded core testing; high level testability; high performance SOC; scan testing; test automation tools; test capability; test logic implementation; test logic validation; Automatic test pattern generation; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Instruments; Logic design; Logic testing; System testing; Very large scale integration;
Conference_Titel :
VLSI Design, 2003. Proceedings. 16th International Conference on
Print_ISBN :
0-7695-1868-0
DOI :
10.1109/ICVD.2003.1183106
