Testing embedded cores and SOCs-DFT, ATPG and BIST solutions

Summary form only given. This tutorial presents a range of design and test techniques and considerations for incorporating high level testability into high performance SOC designs, constructed using embedded cores. Different solutions are proposed around DFT, ATPG and BIST techniques, and their implementation explained from the design and test viewpoints, for different components of SOCs. Capabilities of test automation tools to aid such implementations are explained alongside. Finally, a framework for design planning to assist in test logic implementation and validation, to meet aggressive design cycle times, is presented.