• DocumentCode
    3235409
  • Title

    Specification and design of multi-million gate SOCs

  • Author

    Chandra, Ramesh ; Henkel, Joerg ; Panda, Preeti Ranjan ; Parameswaran, Sri ; Ramachandran, Loganath

  • Author_Institution
    ST Microelectronics, USA
  • fYear
    2003
  • fDate
    4-8 Jan. 2003
  • Firstpage
    18
  • Lastpage
    19
  • Abstract
    Summary form only given. Recent advances in semiconductor technology have made it possible to integrate multi million transistors on a single chip; design and verification teams face several challenges managing the complexity. Some of these challenges include, specification and verification at the functional level, closing early on the system level architecture, extensive simulations of the hardware and software components and finalizing the path to implementation of the entire SOC. This tutorial covers the state-of-the-art in specification, design and verification techniques.
  • Keywords
    circuit simulation; hardware-software codesign; integrated circuit design; integrated circuit modelling; logic design; logic simulation; program verification; specification languages; system-on-chip; SOC design; SOC specification; functional level verification; hardware simulation; hardware/software implementation; multi-million gate SOC; software simulation; specification languages; system level architecture; Computational modeling; Computer architecture; Engineering management; Hardware; Microelectronics; National electric code; Power engineering and energy; Specification languages; System-level design; Technology management;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2003. Proceedings. 16th International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-1868-0
  • Type

    conf

  • DOI
    10.1109/ICVD.2003.1183107
  • Filename
    1183107