A low-current linearity sweet spot in HFETs

Author

Vaitkus, R. ; Nair, V. ; Tehrani, S.

Author_Institution

Phoenix Corp. Res. Lab., Motorola Inc., Tempe, AZ, USA

fYear

1995

fDate

17-19 May 1995

Firstpage

25

Lastpage

28

Abstract

Planar doped HFETs exhibit a narrow bias region of low intermodulation distortion, a linearity sweet spot, at low drain current levels. The bias condition associated with this sweet spot is shown to be near the low-current inflection point of the transconductance versus gate voltage characteristic. It is also shown that the bias condition for the sweet spot can be controlled in dual-gate HFETs. This feature in the HFET characteristics can be exploited to design low-power front-end MMICs with better intercept points for applications in wireless communications

Keywords

MMIC; electric admittance; field effect MIMIC; intermodulation distortion; radio equipment; HFET characteristics; bias condition; dual-gate HFET; gate voltage characteristic; intercept points; low drain current levels; low intermodulation distortion; low-current inflection point; low-current linearity sweet spot; low-power front-end MMIC; planar doped HFET; transconductance; wireless communications; Distortion measurement; HEMTs; Intermodulation distortion; Linearity; MODFETs; Noise figure; System testing; Transconductance; Voltage; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Systems Conference, 1995. Conference Proceedings., IEEE NTC '95

Conference_Location

Orlando, FL

Print_ISBN

0-7803-2591-1

Type

conf

DOI

10.1109/NTCMWS.1995.522856

Filename

522856