0.6V correlators for WLAN receivers

We present low power correlator circuits for direct sequence spread spectrum receivers. We evaluated the effectiveness of three types of logic families (Static CMOS, CP, Domino) in correlator design. The correlator is simple in its implementation using only summer and delay elements. The circuits were implemented using standard threshold voltage transistors in 90 nm CMOS and operated with 0.6 V supply. Conclusions regarding power, delay and area trade-offs are made. Baseline circuits were the static CMOS. Simulation results show that a Domino logic implementation results in a least power consumption and delay for a modest trade-off in area, however this comes at the price of complexity. The CPL implementation results in a 30% decrease in area for the same power consumption with a three times increase in delay. The optimum correlator is a domino logic-based correlator that consumes 1.54 uW of power with a delay of 1.845 ns.