Title :
A genetic algorithm for testable data path synthesis
Author :
Harmanani, H. ; Saliba, R. ; Khoury, M.
Author_Institution :
Dept. of Comput. Sci., Lebanese American Univ., Byblos, Lebanon
Abstract :
A high level synthesis for testability method is presented with the objective to generate testable RTL designs from behavioral descriptions. The approach is formulated as an allocation problem and solved using an efficient genetic algorithm that generates cost-effective testable designs. We follow the allocation method with an automatic test point selection algorithm that trades off design area and delay with test quality. The method has been implemented and design comparisons are reported
Keywords :
circuit optimisation; combinational circuits; data flow graphs; design for testability; genetic algorithms; high level synthesis; integrated circuit design; integrated circuit testing; integrated logic circuits; logic testing; resource allocation; RTL designs; allocation problem; automatic test point selection algorithm; behavioral descriptions; cost-effective testable designs; delay; design area; genetic algorithm; high level synthesis for testability method; table data path synthesis; test quality; Algorithm design and analysis; Automatic testing; Biological cells; Built-in self-test; Circuit testing; Computer science; Delay; Genetic algorithms; High level synthesis; Very large scale integration;
Conference_Titel :
Electrical and Computer Engineering, 2001. Canadian Conference on
Conference_Location :
Toronto, Ont.
Print_ISBN :
0-7803-6715-4
DOI :
10.1109/CCECE.2001.933591
