Title :
Applying cycle-based simulation technique to VITAL as a VHDL gate level standard
Author :
Yaran, Benyamin Hamdin ; Rahmati, Dara ; Zebardast, Abolfazl Salimi
Author_Institution :
Fac. of Eng., Tehran Univ., Iran
Abstract :
Simulation engines are a major part of automatic hardware design process. On the other hand the size and complexity of designs and limitation of the speed of simulation engines leads to the advanced concepts in simulation acceleration and verification. In this paper we introduce an implementation of VITAL cycle-based simulator that uses potential abilities of VITAL standard for fast VHDL gate level simulation
Keywords :
circuit complexity; circuit simulation; formal verification; hardware description languages; integrated circuit design; integrated logic circuits; logic CAD; logic simulation; software standards; VHDL gate level standard; VITAL cycle-based simulator; automatic hardware design process; complexity; cycle-based simulation technique; design; simulation acceleration; simulation engines; verification; Acceleration; Application specific integrated circuits; Circuit simulation; Clocks; Design automation; Engines; Hardware design languages; Libraries; Terminology; Timing;
Conference_Titel :
Electrical and Computer Engineering, 2001. Canadian Conference on
Conference_Location :
Toronto, Ont.
Print_ISBN :
0-7803-6715-4
DOI :
10.1109/CCECE.2001.933592
