Spatial and temporal stability of vision chips including parasitic inductances and capacitances

Author

Kobayashi, Haruo ; Matsumoto, Takashi

Author_Institution

Dept. of Electron. Eng., Gunma Univ., Japan

Volume

2

fYear

1998

fDate

12-15 May 1998

Firstpage

1081

Abstract

There are two dynamics issues in vision chips: (i) the temporal dynamics issue due to the parasitic capacitors in a CMOS chip, and (ii) the spatial dynamics issue due to the regular array of processing elements in a chip. In this paper we consider parasitic inductances as well as parasitic capacitances for a network dynamics model. We show that in some cases the temporal stability condition for the network with parasitic inductances and capacitances is equivalent to that for the network with only parasitic capacitances, but in general they are not equivalent. We also show that the spatial stability conditions are equivalent in both cases

Keywords

CMOS analogue integrated circuits; analogue processing circuits; capacitance; circuit stability; computer vision; inductance; neural chips; CMOS chip; network dynamics model; parasitic capacitors; parasitic inductance; regular array; spatial dynamics; spatial stability; temporal dynamics; temporal stability; vision chips; Boundary conditions; CMOS process; Computer vision; Eigenvalues and eigenfunctions; Linear systems; Neural networks; Parasitic capacitance; Resistors; Stability; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on

Conference_Location

Seattle, WA

ISSN

1520-6149

Print_ISBN

0-7803-4428-6

Type

conf

DOI

10.1109/ICASSP.1998.675456

Filename

675456