A Mixed-Signal Matched-Filter Design and Simulation

A 0.35 mu-CMOS mixed-signal programmable filter suitable for high-rate communication systems is designed and investigated. The proposed filter has analog input and analog-sampled outputs. Filter taps are stored in a digital memory and can be changed on the fly. The filter structure is based on a bank of digitally controlled transconductors along with small capacitors. The employed transconductors are based on simple inverter and thus can be integrated efficiently with the digital parts of a system. A FIR cosine rolloff filter is designed and investigated by simulation in time and frequency domains. The results show that the proposed structure has a good speed-complexity-consumption trade-off.