Title :
A simple testing structure for analog circuits
Author_Institution :
Dept. of Electron. Eng., Nat. Kaohsiung Univ. of Appl. Sci., Kaohsiung, Taiwan
Abstract :
This paper presents a simple current-mode testing structure for analog circuit. The proposed structure is designed by the concept of the switch-current (SI) circuit. The proposed structure moderates the rigorous matching requirement and nonidealities induced by the conventional scan based testing structure. The proposed analog testing structure is divided into two operating modes that are self evaluation mode and built-in test mode. The loading phase and reading phase are both performed to complete the individual operating modes. As a result, the proposed testing structure itself can be evaluated in prior to the actual testing. This structure is digitally controlled and can be configured to accomplish a wider range of analog signal or verify more analog device under test (DUT). Simulation results also demonstrate the effectiveness of the proposed analog testing structure.
Keywords :
analogue integrated circuits; built-in self test; current-mode circuits; integrated circuit testing; analog circuits; analog device under test; analog testing structure; built-in test mode; rigorous matching nonidealities; rigorous matching requirement; scan based testing structure; self evaluation mode; simple current-mode testing structure; switch-current circuit; Analog circuits; Built-in self-test; Loading; Mirrors; Switching circuits; Transistors; analog circuit; built-in test mode; self evaluation mode; switch-current (SI) circuit; testing structure;
Conference_Titel :
Information Security and Intelligence Control (ISIC), 2012 International Conference on
Conference_Location :
Yunlin
Print_ISBN :
978-1-4673-2587-5
DOI :
10.1109/ISIC.2012.6449699