The DDRx memory controller extended for reconfigurable computing

With the popularity of the DDRx memory there are a lot of applications in digital products and platforms and the reconfigurable computing system has potential to accelerate in large amounts of data computing. However, current trend is towards combining a microprocessor with one or many reconfigurable computing units. Thus, the massive data transfer among CPUs, memory modules and reconfigurable accelerators will be a big challenge for system bus. And then the system performance will be limited on the system bus bandwidth. In this paper, we propose the architecture to connect DDRx memory and reconfigurable FPGA directly and it can support the data transfer function between them bypassing system bus, called brain module controller, whose instruction set is created through the extension of DDRx memory controller´s. By the controller functions, we can construct a Software-Hardware co-design platform with memory mapped methods.