Analysis of floating-body-induced leakage current in 0.15 μm SOI DRAM

Author

Terauchi, Mamoru ; Yoshimi, Makoto

Author_Institution

ULSI Res. Center, Toshiba Corp., Kawasaki, Japan

fYear

1996

fDate

30 Sep-3 Oct 1996

Firstpage

138

Lastpage

139

Abstract

Summary form only given. Degradation of the dynamic retention time in SOI DRAMs is a critical issue in the application of SOI technology to memory devices. One possible degradation mode related with the floating-body effect occurs in a non-selected memory cell storing “1” due to a transient lowering of the threshold voltage (Vth) of the transistor associated with a voltage drop of a data line from a precharge level to 0 V. It was reported that this dynamism can induce a leakage current as high as several mA at low voltage regions. In this paper, the possibility of this degradation mode in a 0.15 μm SOI DRAM cell is analyzed in detail considering various device parameters and the design guideline to avoid the degradation is described

Keywords

DRAM chips; MOS memory circuits; capacitance; integrated circuit modelling; leakage currents; silicon-on-insulator; 0.15 micron; SOI DRAM; Si; design guideline; dynamic retention time; floating-body-induced leakage current; memory devices; nonselected memory cell; retention time degradation; threshold voltage lowering; Capacitance; Circuits; Degradation; Guidelines; Leakage current; Random access memory; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1996. Proceedings., 1996 IEEE International

Conference_Location

Sanibel Island, FL

ISSN

1078-621X

Print_ISBN

0-7803-3315-2

Type

conf

DOI

10.1109/SOI.1996.552532

Filename

552532