Fault simulation with PLDs

Author

Gallagher, W.L. ; Yao, Hawkins H. ; Swartzlander, Earl E., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

Volume

1

fYear

1997

fDate

2-5 Nov. 1997

Firstpage

411

Abstract

One measure of the effectiveness of fault tolerance in a circuit is fault coverage, the ratio of the number of faults detectable or correctable to the number of possible faults. Fault simulation can provide an estimate of the fault coverage, but is often prohibitively slow if performed in software. Simulating a faulty circuit using programmable logic devices can speed up the process. Two basic approaches to fault simulation using PLDs are discussed. Fault simulation, for ripple carry adders is carried out in both a PLD and wholly in software and the performance compared.

Keywords

adders; circuit analysis computing; integrated circuit testing; programmable logic devices; software engineering; PLD; circuit fault tolerance; dynamic fault injection; fault coverage; fault simulation; performance; programmable logic devices; ripple carry adders; software; Adders; Application software; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Hardware; Programmable logic devices; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems & Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-8186-8316-3

Type

conf

DOI

10.1109/ACSSC.1997.680279

Filename

680279