VLSI design and implementation of an improved squaring circuit by combinational logic

Author

Abdel-Aty-Zohdy, Hoda S. ; Hiasat, Ahmad A.

Author_Institution

Dept. of Electr. & Syst. Eng., Oakland Univ., Rochester, MI, USA

Volume

1

fYear

1997

fDate

2-5 Nov. 1997

Firstpage

426

Abstract

An improved VLSI squaring circuit, for a Viterbi algorithm, is designed and implemented in the n-well CMOS 2/spl mu/m process. It is faster and more area efficient than conventional and table look-up approaches. In addition it compensates for inaccuracies and noise. The new design is based on combinational logic and the implemented chip reduces the IC area by more than 40% and increases the speed by 100%, as compared to other published designs (Eshraghi et al., 1994). Design considerations, performance evaluations, and test results are presented.

Keywords

CMOS logic circuits; VLSI; combinational circuits; integrated circuit layout; integrated circuit testing; 2 micron; IC area; VLSI design; Viterbi algorithm; combinational logic; implementation; improved squaring circuit; inaccuracies; n-well CMOS 2/spl mu/m process; noise; performance evaluations; speed; test results; CMOS logic circuits; CMOS process; Combinational circuits; Design engineering; Laboratories; Logic design; Microelectronics; Systems engineering and theory; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems & Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-8186-8316-3

Type

conf

DOI

10.1109/ACSSC.1997.680363

Filename

680363