• DocumentCode
    3240778
  • Title

    CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns

  • Author

    Li, Yanjing ; Makar, Samy ; Mitra, Subhasish

  • Author_Institution
    Stanford Univ., Stanford, CA
  • fYear
    2008
  • fDate
    10-14 March 2008
  • Firstpage
    885
  • Lastpage
    890
  • Abstract
    CASP, concurrent autonomous chip self-test using stored test patterns, is a special kind of self-test where a system tests itself concurrently during normal operation without any downtime visible to the end-user. CASP consists of two ideas: 1. Storage of very thorough test patterns in non-volatile memory; and, 2. Architectural and system-level support for autonomous testing of one or more cores in a multi-core system using stored patterns, concurrently with normal system operation, without bringing down the entire system. CASP enables design of robust systems with built-in features for circuit failure prediction, error detection, self-diagnosis and self-repair. Such systems are necessary to overcome major reliability challenges in scaled-CMOS technologies. Implementation of CASP in the OpenSPARC Tl multi-core processor demonstrates its effectiveness and practicality.
  • Keywords
    CMOS integrated circuits; built-in self test; error detection; integrated circuit testing; microprocessor chips; CMOS technologies; autonomous testing; circuit failure prediction; concurrent autonomous chip self-test; error detection; multi-core processor; non-volatile memory; stored test patterns; Aging; Automatic testing; Built-in self-test; Circuit testing; Costs; Nonvolatile memory; Production; Robustness; Sun; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2008. DATE '08
  • Conference_Location
    Munich
  • Print_ISBN
    978-3-9810801-3-1
  • Electronic_ISBN
    978-3-9810801-4-8
  • Type

    conf

  • DOI
    10.1109/DATE.2008.4484786
  • Filename
    4484786