Title :
Design methodology for microcontroller core-based ASIC design
Author :
Lo, Rwei ; Chu, Dante ; Soboleski, A. ; El-Khatib, Monte ; Sakaguchi, Yukio
Abstract :
This paper describes Hitachi´s design methodology for a Microcontroller core-based ASIC. The unique feature of this design methodology is a “Custom CPU Core Compiler” that improves Design Turnaround Time and provides a “user-friendly” environment to interface the CPU with the peripheral blocks. This CPU compiler is available for use with Hitachi´s MicroCBIC ASIC family
Keywords :
Application specific integrated circuits; Circuit testing; Databases; Design methodology; Logic design; Logic testing; Microcontrollers; Random access memory; Read only memory; Read-write memory;
Conference_Titel :
WESCON/'95. Conference record. 'Microelectronics Communications Technology Producing Quality Products Mobile and Portable Power Emerging Technologies'
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2636-9
DOI :
10.1109/WESCON.1995.485248
