Design of per-VC queueing ATM switches

We argue in this paper that ATM switches should be traffic flow oriented and switches should handle each traffic flow separately. We propose a design of per-VC queueing ATM switches which exert precise traffic management on each virtual connection. We introduce a shared-memory based switching architecture which integrates routing and buffering functionalities in the ATM switch. All ATM cells are stored statically in the buffer. It is different from other common approaches which require cells to move through various sorting and routing stages inside the switch. The proposed switching architecture can easily support multicast/broadcast and priority scheduling. No cells will be duplicated in the buffer for multicasting/broadcasting. This paper also presents performance evaluation of the proposed ATM switching architecture in terms of the throughput, queue size distribution, and cell loss probability