Title :
Transistor leakage fault location with IDDQ measurement
Author :
Xiaoqing, Wen ; Tamamoto, Hideo ; Kinoshita, Keizo
Author_Institution :
Min. Coll., Akita Univ., Japan
Abstract :
This paper discusses the problem of locating transistor leakage faults with only IDDQ measurement. A new approach of equivalence fault collapsing is proposed for reducing the number of faults that must be considered. Fault location is performed by using both random and deterministic tests in order to obtain a high diagnostic resolution with a small number of tests. The experimental results show that the diagnosed faults are confined to only a few gates in many cases and that a very high average diagnostic resolution can be achieved for a gate-array circuit
Keywords :
CMOS logic circuits; electric current measurement; fault diagnosis; fault location; field effect transistor circuits; leakage currents; logic arrays; logic testing; CMOS circuit; IDDQ measurement; deterministic tests; diagnosed faults; diagnostic resolution; equivalence fault collapsing; gate-array circuit; random tests; transistor leakage fault location; Circuit faults; Circuit testing; Educational institutions; Fault diagnosis; Fault location; Manufacturing; Monitoring; Physics; Semiconductor device modeling; Voltage;
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
DOI :
10.1109/ATS.1995.485316
